Processor Specifications

Notes

1. The Intel 80186 and 80188 processors were variations of the Intel 8086 and 8088, but they were unsuccessful in sales.
2. The IBM 80386SL contains an integral-cache controller, but the cache memory must be provided outside the chip.
3. The Intel Overdrive P24T and Cyrix 5x86 processors have 64-bit internal data buses and 32-bit external data buses.
4. The Intel Pentium and Pentium Pro processors have 64-bit data buses but only 32-bit registers, meaning that they are not truely 64-bit. In the case of any chip containing MMX instructions, 8 of these utilize 64-bit registers. This makes all MMX-compatible CPUs 64-bit hybrids. Cyrix inparticular, from the 6x86 on, has used parallel floating point instruction execution internally at the 64-bit register level.
5. The Pentium Pro processor was designed heavily toward 32-bit processing. As a result, running Windows 9x/ME will result in a performance hit, compared with earlier Pentium processors. The Pentium Pro works better with Windows NT, 2000, or Linux.
6. The Intel Pentium II Celeron originally came without the L2 cache. The only model to not have the cache was the 300. The newer 300s and later versions contain a 128K L2 cache.
7. The L2 cache on Pentium II cartridge processors runs at only 1/2 the core speed. The L2 cache on Pentium II Xeon processors, however, runs at full core clock speed.
8. The transistor count for the L2 cache of certain processors is listed separately because it is contained within separate chips. If the processor has an integrated L2 cache in one chip, its transistor count is included in the total.
9. The first processor to have Hyperthreading (HT) technology was the Intel Pentium 4 Xeon. Although integrated into one CPU, HT involves having two complete pipelines in parallel, making the processor "appear" to have 2 CPUs. Supposedly, only Windows XP recognizes HT CPUs.
10. Dual-core CPUs have two whole, separate processors integrated into one complete ceramic housing. Quad-core CPUs have four whole, separate processors integrated into one complete ceramic housing. Each separate processor has its own L1 and L2 caches.